| CPC G06F 12/0855 (2013.01) | 24 Claims |
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1. An apparatus comprising:
a set of interfaces from which to received memory requests;
a cache with a cache set; and
processing circuitry configured to:
determine the cache set for a memory request received via an interface from the set of interfaces, the cache set having multiple ways, each way corresponding to a cache line;
detect that a way of the multiple ways is not ready for the memory request;
store a representation of the memory request in a queue of multiple queues based on:
the interface upon which the memory request was received; and
present ways of the cache set;
dequeue entries from the multiple queues in a defined order to determine a next memory request to process, the defined order giving priority to memory requests that match a present way over memory requests that do not match a present way, and the defined order giving priority to memory requests from an external interface over memory requests from an internal interface; and
process the memory request in response to the representation of the memory request being dequeued.
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