CPC G06F 12/0804 (2013.01) [G06F 3/0623 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0253 (2013.01); G06F 12/10 (2013.01); G06F 2212/608 (2013.01); G06F 2212/7205 (2013.01)] | 20 Claims |
1. A memory controller comprising:
an interface to storage;
a memory; and
processing circuitry configured to:
cache a plaintext version of a logical-to-physical (L2P) map portion for the storage in the memory;
modify, via the interface, the storage referred to in the L2P map portion;
update the plaintext version of the L2P map portion, to create an updated version, based on the modification to the storage;
determine that a change in the updated version from a previous version is greater in magnitude than a threshold;
create, in response to the update of the plaintext version of the L2P map portion having the change greater in magnitude than the threshold, an encrypted version from the updated version of the L2P map portion;
store the encrypted version in the memory along with the updated version of the L2P map portion;
provide, to a host device, the encrypted version from the memory in response to a request from the host device for the L2P map portion; and
update the updated version of the L2P map portion, to create an additional updated version, based on the modification to the storage; and
determine that a change in the additional updated version from the updated version is not greater in magnitude than the threshold, wherein an encrypted version of the additional updated version is not created based on the change being not greater in magnitude than the threshold.
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