US 11,914,499 B2
Systems and methods for preparing trace data
Avneep Kumar Goyal, Greater Noida (IN); Thomas Szurmant, Munich (DE); Misaele Marletti, Druento (IT); and Alessandro Daolio, Sannazzaro de' Burgondi (IT)
Assigned to STMicroelectronics Application GMBH, Aschheim-Dornach (DE); STMicroelectronics S.r.l., Agrate Brianza (IT); and STMicroelectronics International N.V., Geneva (CH)
Filed by STMICROELECTRONICS APPLICATION GMBH, Aschheim-Dornach (DE); STMicroelectronics S.r.l., Agrate Brianza (IT); and STMicroelectronics International N.V., Geneva (CH)
Filed on Oct. 29, 2021, as Appl. No. 17/515,212.
Prior Publication US 2023/0133912 A1, May 4, 2023
Int. Cl. G06F 11/36 (2006.01); G06F 11/34 (2006.01); G06F 11/30 (2006.01)
CPC G06F 11/3636 (2013.01) [G06F 11/3082 (2013.01); G06F 11/3466 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A system to provide filtered trace data, the system comprising:
a processor;
a Static Random Access Memory (SRAM) controller;
a first data-preparation circuit coupled with the processor to receive first traced memory-write data from the processor, the first data-preparation circuit configured to filter first unselected traced memory-write data from first selected traced memory-write data;
a second data-preparation circuit coupled with the SRAM controller to receive second traced memory-write data from the SRAM controller, the second data-preparation circuit configured to filter second unselected traced memory-write data from second selected traced memory-write data;
a data-collection network configured to receive the first selected traced memory-write data and the second selected traced memory-write data; and
an output interface coupled with the data-collection network to output the first selected traced memory-write data and the second selected traced memory-write data.