US 11,914,490 B2
Reactive read based on metrics to screen defect prone memory blocks
Harish Reddy Singidi, Fremont, CA (US); Vamsi Pavan Rayaprolu, San Jose, CA (US); Kishore Kumar Muchherla, Fremont, CA (US); Jianmin Huang, San Carlos, CA (US); Xiangang Luo, Fremont, CA (US); and Ashutosh Malshe, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 1, 2021, as Appl. No. 17/492,220.
Application 17/492,220 is a continuation of application No. 16/159,132, filed on Oct. 12, 2018.
Prior Publication US 2022/0019507 A1, Jan. 20, 2022
Int. Cl. G06F 11/20 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/2094 (2013.01) [G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0647 (2013.01); G06F 3/0673 (2013.01); G06F 11/1068 (2013.01); G06F 2201/82 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A system comprising:
one or more memory devices having multiple blocks of memory cells; and
a memory controller including processing circuitry including one or more processors, the memory controller configured to perform operations to:
track multiple metrics associated with memory operations on a block of the multiple blocks, each metric of the multiple metrics being a measurable event of a specified memory operation;
generate a Z-score for each of the multiple metrics;
compare the Z-scores of the multiple metrics to Z-score thresholds for the multiple metrics, providing multiple comparisons; and
control retirement of the block of memory based on at least one of the multiple comparisons and a comparison of a parameter to a parameter threshold, the parameter associated with the metric of the at least one of the multiple comparisons.