US 11,914,481 B2
Hybrid memory system with configurable error thresholds and failure analysis capability
Scott H. Milton, Irvine, CA (US); Jeffrey C. Solomon, Irvine, CA (US); and Kenneth S. Post, Newport Coast, CA (US)
Assigned to NETLIST, INC., Irvine, CA (US)
Filed by Netlist, Inc., Irvine, CA (US)
Filed on Jan. 13, 2023, as Appl. No. 18/154,500.
Application 18/154,500 is a continuation of application No. 17/549,251, filed on Dec. 13, 2021, abandoned.
Application 17/549,251 is a continuation of application No. 16/517,210, filed on Jul. 19, 2019, granted, now 11,200,120, issued on Dec. 14, 2021.
Application 16/517,210 is a continuation of application No. 14/214,652, filed on Mar. 14, 2014, granted, now 10,372,551, issued on Aug. 6, 2019.
Claims priority of provisional application 61/799,556, filed on Mar. 15, 2013.
Claims priority of provisional application 61/799,271, filed on Mar. 15, 2013.
Claims priority of provisional application 61/798,956, filed on Mar. 15, 2013.
Prior Publication US 2023/0418712 A1, Dec. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/14 (2006.01); G06F 11/07 (2006.01); G11C 16/34 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/04 (2006.01)
CPC G06F 11/1458 (2013.01) [G06F 11/073 (2013.01); G06F 11/076 (2013.01); G06F 11/0793 (2013.01); G11C 16/349 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G11C 29/4401 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system having programmable reliability levels, the memory system comprising:
a non-volatile memory (NVM) subsystem comprising a plurality of blocks each including a plurality of pages, each page including a plurality of NVM cells and configured to store an associated number of bytes;
a plurality of programmable registers including first and second programmable threshold registers configured to store first and second programmable threshold values, respectively, wherein the second programmable threshold value is less than the first programmable threshold value; and
a controller coupled to the NVM subsystem and the plurality of programmable registers including the first and second programmable threshold registers, the controller configured to determine if operation reliability for a first memory portion of the NVM subsystem has reached first or second reliability levels,
wherein the first memory portion is a page or a block of the NVM subsystem,
wherein the operation reliability for the first memory portion reaches the first reliability level when a first parameter for the first memory portion matches or exceeds the first programmable threshold value,
wherein the operation reliability for the first memory portion reaches the second reliability level when the first parameter matches or exceeds the second programmable threshold value,
wherein, in response to the operation reliability for the first memory portion reaching the first reliability level, the controller is further configured to perform a first remediation action, and
wherein, in response to the operation reliability for the first memory portion reaching the second reliability level, the controller is further configured to perform a second remediation action.