US 11,914,467 B2
Dynamic control of error management and signaling
Michael Dieter Richter, Ottobrunn (DE); Thomas Hein, Munich (DE); Wolfgang Anton Spirkl, Germering (DE); Martin Brox, Munich (DE); and Peter Mayer, Neubiberg (DE)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Oct. 11, 2022, as Appl. No. 17/963,367.
Application 17/963,367 is a continuation of application No. 17/486,751, filed on Sep. 27, 2021, granted, now 11,494,258.
Application 17/486,751 is a continuation of application No. 16/711,354, filed on Dec. 11, 2019, granted, now 11,138,064, issued on Oct. 5, 2021.
Claims priority of provisional application 62/779,024, filed on Dec. 13, 2018.
Prior Publication US 2023/0030776 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G01K 1/024 (2021.01)
CPC G06F 11/1004 (2013.01) [G01K 1/024 (2013.01); G06F 11/1068 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory array;
first logic associated with the memory array, wherein the first logic is configured to generate a first error correction code for data and detect one or more errors in the data based at least in part on a second command being received from a host device;
second logic associated with the memory array and the first logic, wherein the second logic is configured to correct the one or more errors in the data determined by the first logic; and
third logic associated with the first logic and the second logic, wherein the third logic comprises a counter that is configured to be incremented based at least in part on the first logic detecting the one or more errors in the data.