CPC G06F 1/24 (2013.01) [G06F 1/324 (2013.01); G06F 1/3243 (2013.01); G06F 9/542 (2013.01); G06F 11/1402 (2013.01); G06F 15/7807 (2013.01); G06N 5/043 (2013.01); H04L 9/085 (2013.01)] | 20 Claims |
1. A System on a Chip (SoC), comprising:
an interconnect for handling transactional traffic between a plurality of circuit subsystems on the SoC, the interconnect comprising a port, the plurality of circuit subsystems including a first circuit subsystem configured to initiate a subsystem wake-up sequence to enable the first circuit subsystem to resume normal operation, the subsystem wake-up sequence involving:
the first circuit subsystem sending a wake-up request signal over a link to the interconnect in response to a wake-up trigger event while the first circuit subsystem is in an inoperable state and the link is in a quiescent state, the wake-up trigger event comprising an event related to the first circuit subsystem;
the interconnect, in response to detecting the wake-up request signal from the first circuit subsystem, notifying a system controller, the system controller in an awake state, that the wake-up request signal was detected; and
the system controller, in response to the notifying, sending a command over the interconnect to the first circuit subsystem, the command directing the first circuit subsystem to initiate the subsystem wake-up sequence to exit the inoperable state.
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