US 6,825,526 C1 (12,521st)
Structure for increasing drive current in a memory array and related method
Yue-Song He, San Jose, CA (US); Nian Yang, Mountain View, CA (US); and Zhigang Wang, Sunnyvale, CA (US)
Filed by Yue-Song He, San Jose, CA (US); Nian Yang, Mountain View, CA (US); and Zhigang Wang, Sunnyvale, CA (US)
Assigned to Monterey Research, LLC
Reexamination Request No. 90/015,205, Mar. 3, 2023.
Reexamination Certificate for Patent 6,825,526, issued Nov. 30, 2004, Appl. No. 10/759,809, Jan. 16, 2004.
Ex Parte Reexamination Certificate issued on Feb. 21, 2024.
Int. Cl. H01L 29/788 (2006.01); H10B 41/30 (2023.01); H10B 69/00 (2023.01)
CPC H10B 41/30 (2023.02) [H10B 69/00 (2023.02)]
OG exemplary drawing
AS A RESULT OF REEXAMINATION, IT HAS BEEN DETERMINED THAT:
The patentability of claims 1-20 is confirmed.
1. A memory array comprising:
first and second isolation regions situated in a substrate, said first and second isolation regions being separated by a separation distance;
a trench situated between said first and second isolation regions, said trench defining trench sidewalls and a trench bottom in said substrate;
a tunnel oxide layer situated between said first and second isolation regions, said tunnel oxide layer being situated on said trench sidewalls and said trench bottom;
a channel region situated underneath said tunnel oxide layer, said channel region extending along said trench sidewalls and said trench bottom, said channel region having an effective channel width, wherein said effective channel width corresponds to a height of said trench sidewalls;
wherein said effective channel width is greater than said separation distance between said first and said second isolation regions.