US 12,239,035 B2
Resistive memory cell having a low forming voltage
Hai-Dang Trinh, Hsinchu (TW); Chii-Ming Wu, Taipei (TW); Hsing-Lien Lin, Hsin-Chu (TW); Tzu-Chung Tsai, Hsinchu County (TW); Fa-Shen Jiang, Taoyuan (TW); and Bi-Shen Lee, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 19, 2022, as Appl. No. 17/867,973.
Application 17/867,973 is a division of application No. 16/807,564, filed on Mar. 3, 2020, granted, now 11,527,717.
Claims priority of provisional application 62/893,977, filed on Aug. 30, 2019.
Prior Publication US 2022/0367810 A1, Nov. 17, 2022
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01)
CPC H10N 70/8833 (2023.02) [H10B 63/30 (2023.02); H10N 70/026 (2023.02); H10N 70/063 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/023 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a memory device, comprising:
forming a bottom electrode over a substrate;
forming a data storage structure on the bottom electrode, wherein the data storage structure is co-doped with a first dopant and a second dopant, wherein a first atomic percentage of the first dopant in the data storage structure is different from a second atomic percentage of the second dopant in the data storage structure, wherein the data storage structure is co-doped with the first and second dopants by a single deposition process; and
forming a top electrode on the data storage structure.