US 12,239,032 B2
Memory cells having increased structural stability
Pavan Kumar Reddy Aella, Eagle, ID (US); Kolya Yastrebenetsky, Boise, ID (US); and Masuji Honjo, Boise, ID (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 29, 2022, as Appl. No. 17/733,723.
Application 17/733,723 is a division of application No. 16/147,159, filed on Sep. 28, 2018, granted, now 11,367,833.
Prior Publication US 2022/0263019 A1, Aug. 18, 2022
Int. Cl. H10N 70/20 (2023.01); G11C 13/00 (2006.01); H10B 63/10 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/231 (2023.02) [G11C 13/0004 (2013.01); H10B 63/10 (2023.02); H10N 70/061 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/882 (2023.02); G11C 2213/52 (2013.01); H10N 70/883 (2023.02); H10N 70/884 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A method of manufacturing a memory cell, comprising:
forming a phase change material (PCM) layer on a bottom lamina layer;
forming a top lamina layer on the PCM layer such that the PCM layer is between the bottom lamina layer and the top lamina layer;
forming an electrode layer on the top lamina layer;
forming a first trench through the electrode layer, the top lamina layer and the PCM layer;
forming a dielectric liner layer along on surfaces of the first trench;
extending the first trench through the dielectric liner layer and the bottom lamina layer to form a second trench and to form, from the dielectric liner layer, a dielectric liner on lateral sidewalls of the second trench, the second trench defining an opening; and
filling the opening with a dielectric material.