CPC H10N 60/84 (2023.02) [G11C 11/44 (2013.01); H10N 60/12 (2023.02); H10N 60/805 (2023.02); H10N 69/00 (2023.02)] | 27 Claims |
23. A memory array comprising:
a plurality of addressable memory cells, each memory cell comprising:
a magnetic junction comprising a pair of isolated magnetic layers adapted to assume respectively distinct magnetization vectors; and
a Josephson junction magnetically coupled to the magnetic junction, having a critical current responsive to a resulting joint magnetization vector comprising the superposition of the distinct magnetization vectors;
a set of control lines, configured to independently control the joint magnetization vector of each memory cell; and
a readout configured to produce a signal responsive to the critical current of a respective memory cell.
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