| CPC H10K 59/131 (2023.02) [G09G 3/3233 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01)] | 18 Claims |
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1. An array substrate, comprising:
a plurality of light emitting elements and a plurality of pixel driving circuits configured to drive light emission in the plurality of light emitting elements; and
a plurality of connecting lines connecting the plurality of pixel driving circuits with the plurality of light emitting elements, respectively;
wherein, in a first region, transistors of multiple pixel driving circuits of the plurality of pixel driving circuits are present, and the plurality of light emitting elements are absent; and
in a second region, multiple light emitting elements of the plurality of light emitting elements are present, and transistors of the plurality of pixel driving circuits are absent;
wherein an orthographic projection of a respective connecting line of the plurality of connecting lines on a base substrate intersects with an orthographic projection of at least one row of pixel driving circuits other than the respective pixel driving circuit on the base substrate;
wherein the plurality of connecting lines are arranged in an array comprising rows and columns, the array being at least partially present in the first region and at least partially present in the second region.
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