US 12,238,991 B2
Display substrate comprising sub-pixels in fan-out wiring region and preparation method therefor
Rong Wang, Beijing (CN); Xiangdan Dong, Beijing (CN); Donghui Tian, Beijing (CN); and Fan He, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/772,151
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed May 21, 2021, PCT No. PCT/CN2021/095038
§ 371(c)(1), (2) Date Apr. 27, 2022,
PCT Pub. No. WO2022/241747, PCT Pub. Date Nov. 24, 2022.
Prior Publication US 2024/0147785 A1, May 2, 2024
Int. Cl. H10K 59/131 (2023.01)
CPC H10K 59/131 (2023.02) 20 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
a display area and a non-display area surrounding the display area, the display area comprising a first display region, a second display region and a fan-out wiring region, the second display region being located between the first display region and the fan-out wiring region; and a plurality of data lines located in the display area,
wherein the first display region comprises a plurality of first sub-pixels, the first sub-pixel comprises a first pixel circuit and a first light emitting element, and an orthographic projection of the first pixel circuit on the display substrate is at least partially overlapped with an orthographic projection of the first light emitting element on the display substrate;
the second display region comprises a plurality of second sub-pixels, the second sub-pixel comprises a second pixel circuit and a second light emitting element, and an orthographic projection of the second pixel circuit on the display substrate is at least partially overlapped with an orthographic projection of the second light emitting element on the display substrate;
the first pixel circuit and the second pixel circuit are electrically connected with the plurality of data lines;
the fan-out wiring region comprises a plurality of data fan-out lines and a plurality of third sub-pixels, the third sub-pixel comprises a third light emitting element, at least one second pixel circuit is electrically connected with at least two light emitting elements, the at least two light emitting elements are selected from at least one of the second light emitting element and the third light emitting element, and the plurality of data fan-out lines are electrically connected with the plurality of data lines; and
the display area comprises a first connecting line and a second connecting line, the first connecting line is configured to connect at least one of: the first pixel circuit and an anode of the first light emitting element, the second pixel circuit and an anode of the second light emitting element, and the second pixel circuit and an anode of the third light emitting element; and the second connecting line is configured to connect anodes of the at least two light emitting elements.