a base substrate;

a transistor array layer, located on the base substrate;

a pixel defining layer, located on a side of the transistor array layer facing away from the base substrate; and

touch electrodes, located on a side of the pixel defining layer facing away from the base substrate; wherein

the base substrate has a display region comprising a plurality of sub-pixels; the sub-pixels comprise pixel circuits and light emitting elements; the pixel circuits comprise gate line patterns, data line patterns, and power supply signal line patterns;

an orthogonal projection of at least part of the touch electrodes on the base substrate is a grid;

the plurality of sub-pixels further comprise a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; an area of an opening region of the first color sub-pixel is smaller than an area of an opening region of the third color sub-pixel, and an area of an opening region of the second color sub-pixel is smaller than the area of the opening region of the third color sub-pixel;

wherein the pixel circuits further comprise first capacitors;

an orthogonal projection of a first capacitor in the first color sub-pixel on the base substrate overlaps with the orthogonal projection of the touch electrodes on the base substrate at a first storage overlap area;

an orthogonal projection of a first capacitor in the second color sub-pixel on the base substrate overlaps with the orthogonal projection of the touch electrodes on the base substrate at a second storage overlap area;

an orthogonal projection of a first capacitor in the third color sub-pixel on the base substrate overlaps with the orthogonal projection of the touch electrodes on the base substrate at a third storage overlap area; and

at least one of the first storage overlap area and the second storage overlap area is larger than the third storage overlap area.