US 12,238,940 B2
Deep trench capacitors embedded in package substrate
Nam Hoon Kim, San Jose, CA (US); Teckgyu Kang, Saratoga, CA (US); Scott Lee Kirkman, Menlo Park, CA (US); and Woon-Seong Kwon, Santa Clara, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Sep. 11, 2023, as Appl. No. 18/244,716.
Application 18/244,716 is a division of application No. 16/806,791, filed on Mar. 2, 2020, granted, now 11,784,215.
Prior Publication US 2023/0420494 A1, Dec. 28, 2023
Int. Cl. H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 25/16 (2023.01); H10D 1/68 (2025.01)
CPC H10D 1/716 (2025.01) [H01L 21/486 (2013.01); H01L 23/13 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 25/16 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19102 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method for fabricating a chip package, comprising:
forming one or more cavities in a substrate having (i) a first surface configured to receive an integrated circuit die comprising a core power distribution area located within a particular region and (ii) a second surface opposite the first surface, each cavity being formed in at least one of the first surface or the second surface;
mounting one or more deep trench capacitors in each cavity; and
mounting the integrated circuit die on the first surface, wherein each of the one or more cavities and each of the one or more deep trench capacitors are arranged under a core power distribution area of the integrated circuit die and within a perimeter defined by and located under the particular region of the integrated circuit die, and
wherein the core power distribution area is a partial area of the integrated circuit die.