US 12,238,939 B2
Memory device having two memory stacks over one bottom electrode
Chieh-Fei Chiu, Tainan (TW); Yong-Shiuan Tsair, Tainan (TW); Wen-Ting Chu, Kaohsiung (TW); Yu-Wen Liao, New Taipei (TW); Chin-Yu Mei, Hsinchu (TW); and Po-Hao Tseng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Mar. 31, 2022, as Appl. No. 17/709,845.
Application 17/709,845 is a division of application No. 16/413,716, filed on May 16, 2019, granted, now 11,296,147.
Prior Publication US 2022/0223651 A1, Jul. 14, 2022
Int. Cl. H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10B 63/30 (2023.02) [H10N 70/066 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first bottom electrode having a first portion and a second portion connected to the first portion;
a first memory stack over the first portion of the first bottom electrode, wherein the first memory stack comprises a first resistive switching element and a first top electrode over the first resistive switching element;
a second memory stack over the second portion of the first bottom electrode, wherein the second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element;
a first spacer continuously surrounding the first memory stack and the second memory stack in a first portion of the memory device;
a metal via extending through the first spacer to a top surface of the first bottom electrode in a second portion of the memory device; and
an oxide dielectric layer covering the first memory stack, the second memory stack, and the first bottom electrode, wherein the oxide dielectric layer is in contact with a sidewall of the first bottom electrode, and is interrupted between the first memory stack and the second memory stack.