US 12,238,934 B2
Method of fabricating semiconductor device comprising ferroelectric layer
Tzu-Yu Chen, Kaohsiung (TW); Hsin-Yu Lai, Hsinchu (TW); Sheng-Hung Shih, Hsinchu (TW); Fu-Chen Chang, New Taipei (TW); and Kuo-Chi Tu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 30, 2021, as Appl. No. 17/461,736.
Prior Publication US 2023/0065132 A1, Mar. 2, 2023
Int. Cl. H10B 53/00 (2023.01); H01L 49/02 (2006.01)
CPC H10B 53/00 (2023.02) [H01L 28/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, comprising:
depositing a ferroelectric layer over a substrate;
performing a first ionized physical deposition process to deposit a top electrode layer over and in contact with the ferroelectric layer, wherein the first ionized physical deposition process is performed with an AC bias in a range from about 0 W to about 50 W, and the AC bias does not exceed 50 W to prevent a ratio of non-ferro phase in the ferroelectric layer from increasing, wherein the ferroelectric layer is exposed to ionized metal atoms during the first ionized physical deposition process;
patterning the top electrode layer into a top electrode; and
patterning the ferroelectric layer into a ferroelectric element below the top electrode.