	US 12,238,933 B2
	Semiconductor structures and methods of forming the same
Yu-Chao Lin, Hsinchu (TW); and Chih-Sheng Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 20, 2022, as Appl. No. 17/580,595.
Claims priority of provisional application 63/275,941, filed on Nov. 4, 2021.
Prior Publication US 2023/0140053 A1, May 4, 2023
Int. Cl. H10B 51/30 (2023.01); H01L 23/522 (2006.01); H01L 29/66 (2006.01); H10B 63/10 (2023.01); H10N 70/20 (2023.01)

CPC H10B 51/30 (2023.02) [H01L 23/5226 (2013.01); H01L 29/6656 (2013.01); H10B 63/10 (2023.02); H10N 70/231 (2023.02)]

20 Claims

1. A method of forming a semiconductor structure, comprising:

forming a high-k material layer, a metal-containing gate material layer, and a silicon material layer sequentially on a base layer, wherein the base layer is an interconnect layer structure, and the high-k material layer is in contact with a dielectric material of the interconnect layer structure, and wherein the silicon material layer is an undoped silicon layer;

patterning the silicon material layer and the metal-containing gate material layer to form a metal-containing gate and a silicon layer sequentially on the base layer;

forming a spacer on sidewalls of the metal-containing gate and the silicon layer, and

patterning the high-k material layer by using the spacer and the silicon layer as a mask, so as to form a high-k layer between the base layer and each of the metal-containing gate and the spacer.

6. A method of forming a semiconductor structure, comprising:

forming a high-k material layer and a gate material layer sequentially on a base layer, wherein the base layer is an interconnect layer structure, and the high-k material layer is in contact with a dielectric material of the interconnect layer structure;

patterning the gate material layer to form a gate layer on the base layer;

forming a spacer on a sidewall of the gate layer;

patterning the high-k material layer to form a high-k layer below the gate layer and the spacer;

forming a low-k layer over the base layer, the low-k layer covering the gate layer and the spacer;

forming an opening pattern in the low-k layer, wherein the opening pattern exposes a portion of the gate layer; and

forming a memory layer and a metal layer in the opening pattern,

wherein the method further comprises forming a silicon material layer over the gate material layer before patterning the gate material layer, wherein the silicon material layer is an undoped silicon layer.

12. A method of forming a semiconductor structure, comprising:

forming a high-k material layer, a gate material layer and a silicon material layer sequentially on a base layer, wherein the base layer is an interconnect layer structure, and the high-k material layer is in contact with a dielectric material of the interconnect layer structure, and wherein the silicon material layer is an undoped silicon layer;

patterning the silicon material layer, and the gate material layer to form a gate layer and a silicon layer sequentially on the base layer;

forming a spacer on a sidewall of the gate layer; and

patterning the high-k material layer by using the spacer as a mask, so as to form a high-k layer below the gate layer and the spacer.