US 12,238,932 B2
Ferroelectric memory device, manufacturing method of the ferroelectric memory device and semiconductor chip
Rainer Yen-Chieh Huang, Changhua County (TW); Hai-Ching Chen, Hsinchu (TW); Yu-Ming Lin, Hsinchu (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 10, 2023, as Appl. No. 18/298,342.
Application 18/298,342 is a continuation of application No. 17/352,339, filed on Jun. 20, 2021, granted, now 11,653,501.
Claims priority of provisional application 63/156,958, filed on Mar. 5, 2021.
Prior Publication US 2023/0269947 A1, Aug. 24, 2023
Int. Cl. H10B 51/20 (2023.01); H01L 21/28 (2006.01); H01L 23/528 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H10B 41/23 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 23/5283 (2013.01); H01L 29/40111 (2019.08); H01L 29/516 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/78391 (2014.09); H10B 41/23 (2023.02); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A ferroelectric memory device, comprising:
a gate electrode;
a channel layer, extending along a first side of the gate electrode;
a ferroelectric layer, extending between the gate electrode and the channel layer;
a blocking layer, in direct contact with the channel layer from a side of the channel layer facing toward the ferroelectric layer, and comprising an oxide material doped with nitrogen; and
a pair of source/drain electrodes, separately in contact with the channel layer from a second side of the channel layer.