US 12,238,928 B2
Three-dimensional flash memory with reduced wire length and manufacturing method therefor
Yun Heub Song, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 13, 2023, as Appl. No. 18/154,210.
Application 18/154,210 is a continuation of application No. 16/634,762, granted, now 11,581,327, previously published as PCT/KR2018/006516, filed on Jun. 8, 2018.
Claims priority of application No. 10-2017-0095792 (KR), filed on Jul. 28, 2017.
Prior Publication US 2023/0143256 A1, May 11, 2023
Int. Cl. H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A method of manufacturing a three-dimensional flash memory comprising:
preparing at least two structures each including a plurality of electrode layers and a plurality of interlayer insulating layers which are alternately stacked, and each including a hole penetrating the plurality of electrode layers and the plurality of interlayer insulating layers to extend in one direction;
forming an intermediate circuit layer of silicon on one of the at least two structures;
stacking another of the at least two structures on the one of the at least two structures such that the intermediate circuit layer is between the one of the at least two structures and the other of the at least two structures; and
filling a metal material in a hole of the one of the at least two structures and a hole of the other of the at least two structures to form a common source line.