| CPC H10B 41/20 (2023.02) [G11C 7/18 (2013.01); G11C 8/14 (2013.01); H10B 41/10 (2023.02)] | 20 Claims |
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1. A device comprising:
a first dielectric layer;
a second dielectric layer;
a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall being recessed from the outer sidewall;
a memory layer on the word line, a portion of the memory layer being disposed between the outer sidewall of the word line and the inner sidewall of the word line;
a semiconductor layer on the memory layer, a portion of the semiconductor layer being disposed between the outer sidewall of the word line and the inner sidewall of the word line;
a first metal line on the semiconductor layer;
a second metal line on the semiconductor layer; and
an isolation region between the first metal line and the second metal line.
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