1. A semiconductor memory device comprising n physical banks, each of which is configured to be entirely or partially included in one of a first logic bank or a second logic bank and arranged in a row direction, wherein n is an integer that is greater than or equal to 3, and wherein a proportion of a sum of respective widths of the n physical banks in the row direction to a height of the n physical banks in a column direction is a real number multiple that is not a multiple of 2.