US 12,238,924 B2
Semiconductor device having STI region
Kunihiro Tsubomi, Higashihiroshima (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Mar. 15, 2021, as Appl. No. 17/202,146.
Prior Publication US 2022/0293612 A1, Sep. 15, 2022
Int. Cl. H10B 12/00 (2023.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01)
CPC H10B 12/50 (2023.02) [H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/31053 (2013.01); H01L 21/31116 (2013.01); H01L 21/76224 (2013.01); H01L 29/0649 (2013.01); H10B 12/09 (2023.02)] 9 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a semiconductor substrate having a first trench formed between a memory cell array region on which a plurality of memory cells are formed and a peripheral circuit region on which a peripheral circuit is formed; and
a first insulating film covering an inner wall and a bottom surface of the first trench, wherein the peripheral circuit region is free from the first insulating film,
wherein the inner wall includes a first inner wall positioned on a boundary between the memory cell array region and the first trench and a second inner wall positioned on a boundary between the peripheral circuit region and the first trench, and
wherein the first insulating film continuously covers the second inner wall, the bottom surface, the first inner wall, and the memory cell array region.