US 12,238,919 B2
Semiconductor structure and semiconductor structure manufacturing method
Yuhan Zhu, Hefei (CN); Chuxian Liao, Hefei (CN); and Zhan Ying, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Nov. 22, 2021, as Appl. No. 17/456,091.
Application 17/456,091 is a continuation of application No. PCT/CN2021/106888, filed on Jul. 16, 2021.
Claims priority of application No. 202010963391.2 (CN), filed on Sep. 14, 2020.
Prior Publication US 2022/0085027 A1, Mar. 17, 2022
Int. Cl. H01L 23/528 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/315 (2023.02) [H10B 12/482 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a wordline; and
a first bitline and a second bitline located on two sides of the wordline and a first storage structure and a second storage structure located on the two sides of the wordline, the first bitline and the second bitline being connected to the first storage structure and the second storage structure respectively through a pair of transistors;
an extension direction of the first bitline and an extension direction of the wordline being at an acute or obtuse angle; and, wherein
the transistors comprise a first transistor and a second transistor, two ends of the first transistor are connected to the first bitline and the first storage structure respectively, and two ends of the second transistor are connected to the second bitline and the second storage structure respectively; and
in a cross-section the first bitline and the second storage structure are located on one side of the transistors, and the second bitline and the first storage structure are located on the other side of the transistors.