US 12,238,916 B2
Asymmetric semiconductor memory device having electrically floating body transistor
Yuniarto Widjaja, San Jose, CA (US)
Assigned to Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed by Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed on Jun. 23, 2023, as Appl. No. 18/213,396.
Application 18/213,396 is a continuation of application No. 17/467,400, filed on Sep. 6, 2021, granted, now 11,729,961.
Application 17/467,400 is a continuation of application No. 16/901,543, filed on Jun. 15, 2020, granted, now 11,133,313, issued on Sep. 28, 2021.
Application 16/901,543 is a continuation of application No. 16/102,896, filed on Aug. 14, 2018, granted, now 10,707,209, issued on Jul. 7, 2020.
Application 16/102,896 is a continuation of application No. 15/356,540, filed on Nov. 19, 2016, granted, now 10,074,653, issued on Sep. 11, 2018.
Application 15/356,540 is a continuation of application No. 14/591,454, filed on Jan. 7, 2015, granted, now 9,524,970, issued on Dec. 20, 2016.
Application 14/591,454 is a continuation of application No. 13/244,899, filed on Sep. 26, 2011, granted, now 8,957,458, issued on Feb. 17, 2015.
Claims priority of provisional application 61/485,081, filed on May 11, 2011.
Claims priority of provisional application 61/471,712, filed on Apr. 5, 2011.
Claims priority of provisional application 61/466,940, filed on Mar. 24, 2011.
Prior Publication US 2023/0354581 A1, Nov. 2, 2023
Int. Cl. H10B 12/00 (2023.01); G11C 11/404 (2006.01); H01L 29/73 (2006.01); H01L 29/78 (2006.01)
CPC H10B 12/20 (2023.02) [G11C 11/404 (2013.01); H01L 29/7308 (2013.01); H01L 29/7841 (2013.01); G11C 2211/4016 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A semiconductor memory cell comprising:
a floating body region configured to be charged to a level indicative of a state of the semiconductor memory cell selected from at least first and second states;
a first region in electrical contact with said floating body region;
a second region in electrical contact with said floating body region and spaced apart from said first region;
a gate positioned between said first and second regions;
a first insulating region located above said floating body region;
second insulating regions adjacent to said floating body region;
third and fourth regions located below said second insulating regions;
a buried layer region located below said floating body region, said third and fourth regions and said second insulating regions, and spaced from said second insulating regions,
wherein said third and fourth regions are electrically connected to said buried layer region; and
wherein said floating body region is bounded by said first insulating region, said second insulating regions, said third and fourth regions, and said buried layer region.