US 12,238,915 B2
Method for manufacturing semiconductor structure and same
Kejun Mu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Anhui (CN)
Filed on Dec. 8, 2021, as Appl. No. 17/545,239.
Application 17/545,239 is a continuation of application No. PCT/CN2021/117288, filed on Sep. 8, 2021.
Claims priority of application No. 202110813573.6 (CN), filed on Jul. 19, 2021.
Prior Publication US 2023/0019583 A1, Jan. 19, 2023
Int. Cl. H01L 21/00 (2006.01); H10B 12/00 (2023.01); H01L 23/522 (2006.01)
CPC H10B 12/09 (2023.02) [H10B 12/50 (2023.02); H01L 23/5226 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure comprising an array area, a peripheral area, and a core area, the method comprising:
providing a base;
forming a lower dielectric layer located on the base;
forming a first lower conductive pillar, a second lower conductive pillar and a third lower conductive pillar located within the lower dielectric layer; wherein, the first lower conductive pillar is located in the array area, the second lower conductive pillar is located in the peripheral area, and the third lower conductive pillar is located in the core area;
forming an upper dielectric layer located on the lower dielectric layer, wherein, the upper dielectric layer exposes a top surface of the first lower conductive pillar, a top surface of the second lower conductive pillar and a partial top surface of the third lower conductive pillar; and
forming a first upper conductive pillar, a second upper conductive pillar and a third upper conductive pillar located within the upper dielectric layer; wherein, the first upper conductive pillar and the first lower conductive pillar constitute a first conductive pillar; the second upper conductive pillar and the second lower conductive pillar constitute a second conductive pillar; the third upper conductive pillar and the third lower conductive pillar constitute a third conductive pillar; a top surface area of the third lower conductive pillar is larger than a top surface area of the third upper conductive pillar.