| CPC H10B 12/033 (2023.02) [H01L 29/0673 (2013.01); H01L 29/225 (2013.01); H01L 29/66742 (2013.01); H01L 29/785 (2013.01); H01L 29/78642 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); H10B 12/30 (2023.02); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H01L 2029/7858 (2013.01)] | 20 Claims |
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1. A method of forming a semiconductor transistor, comprising:
forming a contact metal layer over a first interlayer dielectric (ILD) layer;
depositing and removing oxide semiconductor layers to form a selected vertical structure as a channel structure over the contact metal layer, wherein the channel structure extends up from the contact metal layer in a first direction and the channel structure comprises:
a channel region; and
two source/drain regions located on respective sides of the channel region, wherein the channel region and the two source/drain regions are stacked up along the first direction;
depositing a spacer oxide layer, dielectric layer, and gate material sequentially over the channel structure;
removing gate material to form a selected gate structure, wherein the gate structure is configured to surround the channel region;
depositing a second ILD layer and opening vias in the second ILD layer to the gate structure, channel structure, and contact metal layer; and
filling the vias with metal to form contact structures.
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