| CPC H05K 3/368 (2013.01) [H01L 21/4807 (2013.01); H01L 21/485 (2013.01); H01L 21/52 (2013.01); H01L 23/5383 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H05K 1/142 (2013.01); H05K 1/186 (2013.01); H01L 23/5385 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/2929 (2013.01); H01L 2224/29386 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H05K 1/0306 (2013.01); H05K 1/0313 (2013.01); H05K 1/181 (2013.01); H05K 2201/0187 (2013.01); H05K 2201/10378 (2013.01)] | 19 Claims |

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9. A method of manufacturing, comprising:
fabricating a chiplet to insert into a pocket of a circuit board, the chiplet having plural bottom side interconnects to electrically connect to a conductor layer of the circuit board and plural top side interconnects adapted to interconnect with two or more semiconductor chips, wherein the circuit board comprises plural build-up layers, the pocket extending vertically into at least two of the build-up layers and including a portion of the conductor layer exposed during fabricating of the pocket into the at least two build-up layers.
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