US 12,238,827 B2
Base structure and wafer placing device
Yasunori Kawanabe, Kirishima (JP); Yuusaku Ishimine, Aira (JP); and Yoshihiro Okawa, Kirishima (JP)
Assigned to KYOCERA Corporation, Kyoto (JP)
Appl. No. 17/598,798
Filed by KYOCERA Corporation, Kyoto (JP)
PCT Filed Mar. 13, 2020, PCT No. PCT/JP2020/011043
§ 371(c)(1), (2) Date Sep. 27, 2021,
PCT Pub. No. WO2020/195930, PCT Pub. Date Oct. 1, 2020.
Claims priority of application No. 2019-063621 (JP), filed on Mar. 28, 2019.
Prior Publication US 2022/0201804 A1, Jun. 23, 2022
Int. Cl. H05B 3/28 (2006.01); H05B 1/02 (2006.01); H01L 21/683 (2006.01)
CPC H05B 3/28 (2013.01) [H05B 1/0233 (2013.01); H01L 21/683 (2013.01); H05B 2203/016 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A base structure comprising:
a base, a first conductor layer, and a via conductor,
the base having a first surface and a second surface positioned opposite to the first surface,
the first conductor layer being positioned along the first surface in the base,
the via conductor intersecting and being coupled to the first conductor layer in the base,
the via conductor including,
in a section that includes the via conductor and that extends in a first direction perpendicular to the first surface,
a first part whose length in the first direction is larger than a thickness of the first conductor layer,
a second part whose length in the first direction is larger than the thickness of the first conductor layer, the second part being continuous with the first part and having an outer edge including at least a portion that is displaced from an outer edge of the first part when viewed in the first direction, and
a third part facing the first part and coupled to the first conductor layer with the first conductor layer interposed between the third part and the first part.