| CPC H04W 72/21 (2023.01) [H04L 1/0057 (2013.01); H04L 1/0061 (2013.01)] | 20 Claims |
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1. A processing system comprising:
a plurality of processing engines, wherein the processing engines include functional units configured to execute an instruction having an input virtual address and an output virtual address, the plurality of processing engines including:
a first processing engine having a plurality of encoder functional units configured to execute a plurality of channel coding instructions to encode a code block, wherein different ones of the plurality of encoder functional units are configured to execute different channel coding instructions from the plurality of channel coding instructions; and
a second processing engine having a mapping functional unit configured to execute a mapping instruction to map at least a portion of a code block to one or more modulation symbols in a constellation;
a plurality of buffers coupled to the plurality of processing engines, wherein different buffers of the plurality of buffers are mapped to different virtual addresses in a virtual address space, the plurality of buffers including an encoder input buffer, an encoder output buffer, and a symbol buffer;
a control processor coupled to the processing engines and configured to dispatch a sequence of instructions to the processing engines to encode a plurality of code blocks including a physical uplink shared channel (PUSCH) code block and a physical uplink control channel (PUCCH) code block, wherein the sequence of instructions for a particular code block includes a selected channel coding instruction selected from the plurality of channel coding instructions having an input virtual address that maps to a first region in the encoder input buffer and an output virtual address that maps to a first region in the encoder output buffer and a mapping instruction having an input virtual address that maps to the first region in the encoder output buffer and an output virtual address that maps to a region in the symbol buffer; and
an interlock controller coupled to the plurality of processing engines and configured to manage data dependencies based on the input virtual addresses and the output virtual addresses of the instructions.
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