a memory; and

one or more processors coupled to the memory, the one or more processors configured to:

receive a grant that schedules multiple downlink communications, wherein the grant includes multiple start and length indicator values (SLIVs) that indicate respective time domain resource allocations (TDRAs) for the multiple downlink communications and a feedback timing indicator that indicates timing of uplink feedback communications for the multiple downlink communications;

determine, based at least in part on the SLIVs and the feedback timing indicator, that there is a conflict between a timing of a first uplink feedback communication for at least one first downlink communication of the multiple downlink communications and a TDRA for a second downlink communication of the multiple downlink communications; and

adjust at least one of the TDRA for the second downlink communication or the timing of the first uplink feedback communication based at least in part on the timing of the first uplink feedback communication, to determine an adjusted TDRA for the second downlink communication and a gap for the first uplink feedback communication and on determining that there is a conflict between the timing of the first uplink feedback communication and the TDRA for the second downlink communication.