| CPC H04W 52/0209 (2013.01) [H04B 7/0686 (2013.01); H04B 7/04 (2013.01); Y02D 30/70 (2020.08)] | 9 Claims |
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1. An apparatus, comprising:
a switchable architecture (SA) analog-to-digital conversion (ADC) system, comprising a plurality of different quantization resolution (QR), selectively enableable-disableable (SED) ADC systems, including at least a SED first QR ADC system and a SED second QR ADC system, wherein a first QR is lower than a second QR;
a coupler circuit configured to couple to a plurality of antenna elements, including at least a first antenna element and a second antenna element, and to couple first antenna signals from the first antenna element concurrently to the SED first QR ADC system and to the SED second QR ADC system, concurrently with coupling second antenna signals from the second antenna element concurrently to the SED first QR ADC system and to the SED second QR ADC system;
a processor, configured to
selectively configure the SA ADC system to a first QR operating architecture comprising the SED second QR ADC system disabled concurrent with the SED first QR ADC system enabled and outputting first QR samples of the first antenna signals and the second antenna signals,
selectively configure the SA ADC system to a second QR operating architecture comprising the SED first QR ADC system disabled concurrent with the SED second QR ADC system enabled and outputting second QR samples of the first antenna signals and the second antenna signals,
selectively perform a first QR sample-based processing, using the first QR samples of the first antenna signals, or the first QR samples of the second antenna signals, or both, and
selectively perform a second QR sample-based processing, using the second QR samples of the first antenna signals, or the second QR samples of the second antenna signals, or both.
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