a pixel array including a plurality of pixels, each of the plurality of pixels including a first photodiode and a second photodiode, the first photodiode having a first light receiving area, the second photodiode having a second light receiving area greater than the first light receiving area, each of the plurality of pixels configured to output a first pixel signal based on a first conversion gain by using the second photodiode in a first period, output a second pixel signal based on a second conversion gain by using the second photodiode in a second period, output a third pixel signal based on the first conversion gain by using the first photodiode in a third period, and output a fourth pixel signal based on the second conversion gain by using the first photodiode in a fourth period;

an analog-to-digital converter (ADC) circuit configured to output a digital signal by performing sampling on a reset signal and an image signal of each of the first pixel signal, the second pixel signal, the third pixel signal, and the fourth pixel signal; and

a timing controller configured to control an operation of the ADC circuit,

wherein the first conversion gain is higher than the second conversion gain,

wherein the timing controller is configured to adjust a sampling count and a number of sampling bits associated with the sampling differently for each of the first period, the second period, the third period, and the fourth period, and

wherein the timing controller includes a register for adjusting the sampling count and the number of sampling bits.