a controller;

a sensor array comprising a plurality of CMOS sensor pixels, wherein the sensor array is configured to supply one of a plurality of analog sensor signals at each of a sequence of sample times, wherein at each of the sample times, the one of the plurality of analog sensor signals is derived from one or more of the plurality of CMOS sensor pixels;

present state decision circuitry configured to compare the one of the plurality of analog sensor signals for each of the sequence of sample times with a respective controller-selected reference voltage and to generate therefrom a respective single state decision signal; and

a pattern recognizer configured to assert a pattern recognition signal whenever a plurality of sequentially generated single state decision signals matches a currently active one of a set of one or more reference sequences of single state decision signals,

wherein the controller is configured to assert a host system trigger signal when the pattern recognition signal is asserted a predefined number of times in sequence.