a Central Processing Unit (CPU), a hardware detection module, a write control module, a read control module, and an First In First Out (FIFO) array module, wherein the FIFO array module comprises a selection switch;

the CPU is configured to send a first enable signal to the hardware detection module, the read control module, and the selection switch;

in response to receiving the first enable signal, the selection switch is configured to select to write test data into the FIFO array module through the hardware detection module;

in response to receiving the first enable signal, the hardware detection module is configured to write test data into the FIFO array module;

in response to receiving the first enable signal, the read control module is configured to read the test data from the FIFO array module, and transmit the read test data to the hardware detection module; and

the hardware detection module is further configured to compare the read test data with the test data written into the FIFO array module, determine, according to a comparison result, a compression format supported by a current video compression system, and send the compression format supported by the current video compression system to the CPU.