US 12,238,221 B2
Cryptographic system memory management
David M. Durham, Beaverton, OR (US); Rajat Agarwal, Portland, OR (US); Siddhartha Chhabra, Portland, OR (US); Sergej Deutsch, Hillsboro, OR (US); Karanvir S. Grewal, Hillsboro, OR (US); and Ioannis T. Schoinas, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Dec. 6, 2021, as Appl. No. 17/542,842.
Application 17/542,842 is a continuation of application No. 16/689,575, filed on Nov. 20, 2019, granted, now 11,196,565.
Application 16/689,575 is a continuation of application No. 15/816,901, filed on Nov. 17, 2017, granted, now 10,594,491, issued on Mar. 17, 2020.
Application 15/816,901 is a continuation in part of application No. 14/998,054, filed on Dec. 24, 2015, granted, now 9,990,249, issued on Jun. 5, 2018.
Prior Publication US 2022/0094553 A1, Mar. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 9/32 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G06F 12/0886 (2016.01); G06F 12/14 (2006.01); G06F 21/78 (2013.01); G06F 21/79 (2013.01); G11C 29/52 (2006.01); H04L 9/06 (2006.01); H04L 9/08 (2006.01); G11C 29/44 (2006.01)
CPC H04L 9/3242 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 11/1068 (2013.01); G06F 11/108 (2013.01); G06F 12/0886 (2013.01); G06F 12/14 (2013.01); G06F 12/1408 (2013.01); G06F 21/78 (2013.01); G06F 21/79 (2013.01); G11C 29/52 (2013.01); H04L 9/0631 (2013.01); H04L 9/0643 (2013.01); H04L 9/0894 (2013.01); G06F 2212/401 (2013.01); G11C 2029/4402 (2013.01); H04L 2209/34 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of cores; and
a memory controller coupled with the plurality of cores, the memory controller to:
decrypt encrypted data to generate decrypted data and decrypt a block correction value in response to a read operation to one or more memory devices, the decrypted data comprising a plurality of data blocks, and the decrypted block correction value comprising a value to repair a data block of the plurality of data blocks;
determine whether the decrypted block correction value matches a result of an XOR operation performed on at least two data blocks of the plurality of data blocks; and
transmit the decrypted data to a cache memory based on a determination that the decrypted block correction value matches the result of the XOR operation performed on the at least two data blocks of the plurality of data blocks.