US 12,237,963 B2
Synchronization signal block patterns for higher subcarrier spacing
Iyab Issam Sakhnini, San Diego, CA (US); Tao Luo, San Diego, CA (US); Jing Sun, San Diego, CA (US); and Xiaoxia Zhang, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 29, 2022, as Appl. No. 17/956,224.
Claims priority of provisional application 63/251,541, filed on Oct. 1, 2021.
Prior Publication US 2023/0106224 A1, Apr. 6, 2023
Int. Cl. H04L 27/26 (2006.01); H04L 5/00 (2006.01); H04W 72/0446 (2023.01)
CPC H04L 27/2666 (2013.01) [H04L 5/0048 (2013.01); H04W 72/0446 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A network entity configured for wireless communications, comprising:
memory comprising computer-executable instructions; and
one or more processors configured to execute the computer-executable instructions and cause the network entity to:
transmit signaling indicating a synchronization signal block (SSB) pattern that identifies SSB slots for sweeping a set of SSB beams over one or more SSB bursts with configurable gaps between at least some of the SSB slots, wherein each of the configurable gaps comprises one or more gap slots, and wherein a quantity of the one or more gap slots is determined based on a subcarrier spacing (SCS) associated with SSBs; and
transmit the SSBs in accordance with the pattern.