CPC H04B 10/6164 (2013.01) [H04B 10/07951 (2013.01); H04B 10/25759 (2013.01); H04B 10/516 (2013.01); H04B 10/616 (2013.01); H04L 1/1657 (2013.01); H04L 7/0075 (2013.01); H04L 25/03305 (2013.01); H04L 25/03331 (2013.01); H04L 27/0014 (2013.01); H04L 27/2662 (2013.01); H04L 69/22 (2013.01); H04B 10/6161 (2013.01); H04L 2027/0026 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
an analog to digital conversion circuitry operable to receive data comprising frames and output digitized data corresponding to the received data; and
a digital signal processor operable to:
receive the digitized data from the analog to digital conversion circuitry;
determine a location of a frame header associated with one of the frames, the location having a probability that satisfies a probability threshold; and
estimate a frequency offset associated with the digitized data using the location of the frame header,
wherein the digital signal processor comprises an AND logic circuit operable to receive confirmation data associated with each subcarrier in the digitized data and to set a barrel shifter flag to a first value when confirmation data for each subcarrier indicates that a framer index estimation associated with the subcarrier is confirmed.
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