US 12,237,868 B2
Service and power control orchestrator
Baranidhar Ramanathan, Karnataka (IN); Ashok Kunjidhapatham, Devarachikkanahalli (IN); Sanjeev Ramachandran, Karnataka (IN); Jonathan Buset, San Jose, CA (US); Nikhil Satyarthi, Yelahanka (IN); Bhupathi Rao Yellinedi, Bangalore (IN); Badareenath Alur Sreenivasacharya, Bangalore (IN); Anil Naduvile Veedu, Kannur (IN); Aryabhata Deshpande, Bommanahalli (IN); Servesh Singh, Bangalore (IN); and Dinesh Kumar Parkasam, Madurai (IN)
Assigned to Infinera Corporation, San Jose, CA (US)
Filed by Infinera Corp., San Jose, CA (US)
Filed on Feb. 2, 2023, as Appl. No. 18/163,636.
Claims priority of provisional application 63/305,779, filed on Feb. 2, 2022.
Prior Publication US 2023/0261749 A1, Aug. 17, 2023
Int. Cl. H04B 10/27 (2013.01); H04B 10/294 (2013.01); H04J 14/02 (2006.01)
CPC H04B 10/271 (2013.01) [H04B 10/294 (2013.01); H04J 14/0221 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A network element, comprising:
a processor;
a first line port optically coupled to a first optical fiber link carrying a first optical signal having a first plurality of passbands;
a wavelength selective switch in optical communication with the first line port, the wavelength selective switch including a multiplexer, a demultiplexer, and one or more control block, and being operable to selectively switch the first optical signal into a second optical signal having a second plurality of passbands, the one or more control block operable to control one or more of: the multiplexer and the demultiplexer;
a second line port optically coupled to a second optical fiber link and operable to carry the second optical signal having the second plurality of passbands, the second line port in optical communication with the wavelength selective switch; and
a memory comprising a non-transitory processor-readable medium storing an orchestrator application, an optical topology and switching abstraction component, one or more service component, and storing processor-executable instructions that when executed by the processor cause the processor to:
store, by the optical topology and switching abstraction component, a logical ROADM model of the network element, the logical ROADM model having a connectivity matrix associating a cross-connection between a first logical line port associated with the first line port and a second logical line port associated with the second line port;
receive, by the orchestrator application, a communication from the one or more service component, the communication being associated with the one or more control block based on the logical ROADM model; and
transmit, to the one or more control block of the wavelength selective switch, one or more service loading sequence based on the logical ROADM model and the communication to cause the wavelength selective switch to control one or more of: the multiplexer via multiplexer WSS controls and the demultiplexer via demultiplexer WSS controls.