US 12,237,861 B2
Devices and methods related to radio-frequency filters on silicon-on-insulator substrate
James Phillip Young, Cedar Rapids, IA (US)
Assigned to Skyworks Solutions, Inc., Irvine, CA (US)
Filed by SKYWORKS SOLUTIONS, INC., Irvine, CA (US)
Filed on Nov. 13, 2023, as Appl. No. 18/508,159.
Application 18/508,159 is a continuation of application No. 17/666,446, filed on Feb. 7, 2022, granted, now 11,817,895.
Application 17/666,446 is a continuation of application No. 16/819,142, filed on Mar. 15, 2020, granted, now 11,245,433, issued on Feb. 8, 2022.
Application 16/819,142 is a continuation of application No. 15/192,812, filed on Jun. 24, 2016, granted, now 10,594,355, issued on Mar. 17, 2020.
Claims priority of provisional application 62/187,174, filed on Jun. 30, 2015.
Prior Publication US 2024/0154639 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04B 1/40 (2015.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/66 (2006.01); H01L 25/065 (2023.01)
CPC H04B 1/40 (2013.01) [H01L 23/49827 (2013.01); H01L 23/66 (2013.01); H01L 24/92 (2013.01); H01L 25/0655 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6655 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/1329 (2013.01); H01L 2224/133 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/92222 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A wireless device comprising:
an antenna configured to transmit and receive a signal;
a transceiver in communication with the antenna; and
a front-end module including a wafer level chip scale package, the wafer level chip scale package including a semiconductor die that includes an integrated circuit, a first side and a second side, and a plurality of vias, each via configured to provide an electrical connection between the first side and the second side of the semiconductor die, the wafer level chip scale package further including a filter device mounted on the first side of the semiconductor die, the filter device in communication with the integrated circuit, the integrated circuit implemented in a layer on the first side of the semiconductor die and at least some of the vias coupled with the integrated circuit to support an electrical connection between the integrated circuit and mounting features on the second side of the semiconductor die.