US 12,237,846 B2
Systems for error reduction of encoded data using neural networks
Fa-Long Luo, San Jose, CA (US); and Jaime Cummins, Bainbridge Island, WA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jan. 23, 2023, as Appl. No. 18/158,332.
Application 18/158,332 is a continuation of application No. 17/302,228, filed on Apr. 27, 2021, granted, now 11,563,449.
Prior Publication US 2023/0163788 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/37 (2006.01); G06F 7/544 (2006.01); G06N 3/08 (2023.01)
CPC H03M 13/37 (2013.01) [G06F 7/5443 (2013.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory configured to store encoded data; and
a neural network configured to receive, from the memory, the encoded data including at least one error bit and further configured to mix the encoded data received from the memory with at least a portion of a plurality of coefficients selected for error reduction of data retrieved from the memory to generate an estimate of an error-reduced version of the encoded data, wherein the neural network comprises at least one stage configured to provide delayed versions of respective outputs and mix the delayed versions of the respective outputs with at least a portion of the encoded data.