US 12,237,844 B2
Error detection and classification at a host device
Aaron P. Boehm, Boise, ID (US); and Scott E Schaefer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 7, 2022, as Appl. No. 17/961,805.
Prior Publication US 2024/0120947 A1, Apr. 11, 2024
Int. Cl. H03M 13/15 (2006.01); H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC H03M 13/159 (2013.01) [H03M 13/1105 (2013.01); H03M 13/611 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method, comprising:
communicating, from a host device, a read command for a codeword stored at a memory device;
receiving, at the host device based at least in part on communicating the read command, the codeword and an error detection bit that indicates whether the memory device detected a first type of error in the codeword;
generating, by the host device based at least in part on a first set of parity bits received from the memory device and on a second set of parity bits generated by the host device, syndrome bits for the received codeword that indicate whether the codeword has a second type of error; and
determining, by the host device, an error status of the codeword based at least in part on the error detection bit received from the memory device and the syndrome bits generated by the host device.