US 12,237,843 B1
Comparator and analog-to-digital converter
Daiguo Xu, Chongqing (CN); Hequan Jiang, Chongqing (CN); Ruzhang Li, Chongqing (CN); Jian'an Wang, Chongqing (CN); Guangbing Chen, Chongqing (CN); Dongbing Fu, Chongqing (CN); Yuxin Wang, Chongqing (CN); Shiliu Xu, Chongqing (CN); and Zicheng Xu, Chongqing (CN)
Assigned to NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing (CN); and Chongqing GigaChip Technology Co., Ltd., Chongqing (CN)
Appl. No. 18/020,085
Filed by NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing (CN); and Chongqing GigaChip Technology Co., Ltd., Chongqing (CN)
PCT Filed Aug. 31, 2020, PCT No. PCT/CN2020/112380
§ 371(c)(1), (2) Date Feb. 7, 2023,
PCT Pub. No. WO2022/027750, PCT Pub. Date Feb. 10, 2022.
Claims priority of application No. 202010788486.5 (CN), filed on Aug. 7, 2020.
Int. Cl. H03M 1/38 (2006.01); H03K 5/24 (2006.01); H03M 1/00 (2006.01); H03M 1/12 (2006.01); H03M 1/44 (2006.01)
CPC H03M 1/44 (2013.01) [H03K 5/2481 (2013.01); H03M 1/002 (2013.01); H03M 1/125 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A comparator, comprising
an input unit, a load unit, a control switch, and an adjustment unit, wherein
input ends of the input unit are connected to a first input signal and a second input signal;
the load unit is connected to the input unit, and the load unit comprises a pair of gain adjustment transistors, wherein gate voltages of the pair of gain adjustment transistors are adjusted to change a gain of the comparator; and
the adjustment unit is connected to the input unit, and the gate voltages of the pair of gain adjustment transistors are adjusted according to an enable state of the control switch;
wherein the load unit further comprises a pair of first offset transistors and a pair of second offset transistors, and the pair of first offset transistors and the pair of second offset transistors are connected to the input unit in parallel;
wherein the pair of first offset transistors comprise a first transconductance and a first output impedance, and the pair of second offset transistors comprise a second transconductance and a second output impedance;
wherein the first transconductance and the second transconductance offset each other according to the enable state of the control switch, or the first output impedance and the second output impedance offset each other according to the enable state of the control switch.