US 12,237,839 B2
Delay locked loop and memory
Siman Li, Hefei (CN); and Yoonjoo Eom, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 13, 2023, as Appl. No. 18/448,946.
Application 18/448,946 is a continuation of application No. PCT/CN2022/123835, filed on Oct. 8, 2022.
Claims priority of application No. 202211006012.6 (CN), filed on Aug. 22, 2022.
Prior Publication US 2024/0063802 A1, Feb. 22, 2024
Int. Cl. H03L 7/087 (2006.01); H03K 19/21 (2006.01); H03L 7/183 (2006.01)
CPC H03L 7/087 (2013.01) [H03K 19/21 (2013.01); H03L 7/183 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A delay locked loop, comprising:
a preprocessing module configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal;
a first regulable delay line configured to receive the first clock signal, regulate and transmit the first clock signal, and output a first target clock signal;
a second regulable delay line configured to receive the second clock signal, regulate and transmit the second clock signal, and output a second synchronization clock signal; and
a first regulation module configured to receive the first target clock signal and the second synchronization clock signal, regulate delay of the second synchronization clock signal based on the first target clock signal, and output a second target clock signal,
wherein a phase difference between the first target clock signal and the second target clock signal is a preset value.