a glitch rejection circuit including n m-stage inverters coupled in series, and configured to receive an input signal and perform an inverting operation on the input signal to generate an output signal and adjust switching threshold voltages of the n m-stage inverters to generate the glitch-removed output signal, when a glitch occurs in the input signal;

a level detection circuit configured to detect a logic level of the output signal provided from the glitch rejection circuit to generate a level detection signal and a complementary level detection signal; and

a voltage signal generation circuit configured to receive the level detection signal, and the complementary level detection signal to generate control voltage signals and provide the control voltage signals to the glitch rejection circuit,

wherein n is a natural number and m is an even number greater than or equal to 2, and

wherein each inverter of the n m-stage inverters adjusts its switching threshold voltage in response to a corresponding control voltage signal of the control voltage signals, the corresponding control voltage signal switching between a first power voltage level and a second power voltage level based on the level detection signal and the complementary level detection signal.