an input node and an output node;

an attenuation path including a first switch, a first node, a plurality of attenuation blocks arranged in series, a second node, and a second switch between the input node and the output node, each attenuation block configured to provide a single resistance when providing attenuation, the attenuation block including a bypass switch configured to be on or off to thereby allow switchable bypassing of the single resistance, the bypass switch providing a single local off-capacitance when off, each of at least some of the attenuation blocks including a local phase compensation circuit configured to compensate for the single local off-capacitance of the respective bypass switch;

a global bypass path implemented between the input node and the output node to be parallel with the attenuation path, the global bypass path including a global bypass switch configured to be on or off to thereby allow switchable bypassing of the attenuation path including the first and second switches without incurring losses associated with the first and second switches, the global bypass switch having a global off-capacitance when off, each of the first and second switches of the attenuation path configured to be off when the global bypass switch is on, and on when the global bypass switch is off; and

a global phase compensation circuit implemented between the first node and the second node, and configured to compensate for the global off-capacitance of the global bypass switch, each of the first and second switches implemented as a single-pole-single-throw switch configured to be on when the global bypass switch is off, the global phase compensation circuit configured to provide a fixed compensation phase value for the global off-capacitance of the global bypass switch and not for any of the first and second switches.