	US 12,237,813 B2
	Power amplifier equalizer
Daoud Salameh, Reading (GB)
Assigned to Murata Manufacturing Co., Ltd., Nagaokakyo (JP)
Filed by Murata Manufacturing Co., Ltd., Kyoto (JP)
Filed on Nov. 7, 2023, as Appl. No. 18/503,814.
Application 18/503,814 is a continuation of application No. 17/165,198, filed on Feb. 2, 2021, granted, now 11,817,827.
Prior Publication US 2024/0146249 A1, May 2, 2024
Int. Cl. H03F 3/45 (2006.01); H03F 1/02 (2006.01); H03F 1/32 (2006.01); H03F 3/213 (2006.01)

CPC H03F 1/0233 (2013.01) [H03F 1/3211 (2013.01); H03F 3/213 (2013.01); H03F 3/45264 (2013.01)]

16 Claims

1. A method of equalizing a differential amplifier including a plurality of field-effect transistors (FETs), the method including:

(a) providing a first main FET including a gate configured to receive a first input signal, a drain configured to provide a first amplified output signal, and a source configured to be coupled to circuit ground;

(b) providing a second main FET including a gate configured to receive a second input signal, a drain configured to provide a second amplified output signal, and a source configured to be coupled to circuit ground;

(d) coupling an equalization circuit to the respective gates and drains of the first and second FETs, wherein the equalization circuit includes:

(1) a first equalization transistor including a drain coupled to the drain of the first main FET, a source coupled to the gate of the second main FET, and a gate configured to be coupled to a first bias voltage source; and

(2) a second equalization transistor including a drain coupled to the drain of the second main FET, a source coupled to the gate of the first main FET, and a gate configured to be coupled to a second bias voltage source; and

(b) altering a bias voltage to the respective gates of the first and second main FETs in proportion to a power level present at the respective drains of the second and first main FETs, as determined by the equalization circuit.