US 12,237,662 B2
Short circuit protection
Eung Jung Kim, Allen, TX (US); and Wenchao Qu, Plano, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Sep. 18, 2023, as Appl. No. 18/469,109.
Application 18/469,109 is a continuation of application No. 17/514,774, filed on Oct. 29, 2021, granted, now 11,799,281.
Claims priority of provisional application 63/184,005, filed on May 4, 2021.
Prior Publication US 2024/0006869 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H02H 3/08 (2006.01); H02H 1/06 (2006.01); H02H 9/02 (2006.01)
CPC H02H 3/08 (2013.01) [H02H 1/06 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for controlling a power circuit, comprising:
enabling the power circuit;
determining, by a current sense component, whether an output current of the power circuit is greater than a first current limit threshold;
reducing, using a current limiting circuit coupled to a power switch, the output current in response to the output current being greater than the first current limit threshold;
determining, by an over-current protection circuit, whether the output current is greater than a second current limit threshold;
decoupling the current limiting circuit from the power switch in response to the output current being greater than the second current limit threshold;
determining, by an over-current protection circuit after the decoupling the current limiting circuit, whether the output current is greater than the second current limit threshold;
coupling the current limiting circuit to the power switch in response to the output current being less than the second current limit threshold; and
limiting an increase in voltage across the power switch using a voltage clamp circuit that includes:
a bi-polar junction transistor (BJT) having a collector, an emitter, and a base, the base configured to receive a reference voltage, and the emitter coupled to a drain of the power switch;
a first field effect transistor (FET) having a first FET drain, a first FET gate, and a first FET source, the first FET gate coupled to the collector, and the first FET source coupled to the collector through a first resistor;
a second FET having a second FET drain, a second FET source, and a second FET gate, wherein the second FET drain and the second FET gate are coupled to the first FET drain, and the second FET source is coupled to a ground terminal;
a third FET having a third FET drain, a third FET source, and a third FET gate, wherein the third FET gate is coupled to the first FET drain, the third FET drain is coupled to a gate of the power switch, and the third FET source is coupled to the ground terminal; and
a fourth FET having a fourth FET drain, a fourth FET source, and a fourth FET gate, wherein the fourth FET gate is coupled to the collector, the fourth FET source is coupled to the collector through the first resistor, and the fourth FET drain is coupled to the ground terminal through a second resistor, wherein a negative output detection signal is provided at the fourth FET drain.