US 12,237,620 B2
Device-to-device connection with multiple parallel ground pins
Xiang Li, Portland, OR (US); and George Vergis, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 26, 2021, as Appl. No. 17/214,397.
Prior Publication US 2021/0313744 A1, Oct. 7, 2021
Int. Cl. H01R 13/6471 (2011.01); H01R 12/73 (2011.01); H01R 12/57 (2011.01); H01R 13/03 (2006.01)
CPC H01R 13/6471 (2013.01) [H01R 12/737 (2013.01); H01R 12/57 (2013.01); H01R 13/03 (2013.01); H01R 2201/06 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first signal pin;
a second signal pin; and
multiple parallel ground pins positioned between the first and second signal pins, the multiple parallel ground pins coupled to a first single pin contact region coupled to a first device and a second single pin contact region coupled to a second device, wherein
the first device comprises a motherboard,
the first single pin contact region is coupled to a surface mount technology (SMT) connector of the motherboard,
the second device comprises a dual in-line memory module (DIMM),
the first device is oriented perpendicular to the second device,
the second single pin contact region is coupled to a gold finger connector in the DIMM,
a first leg of the multiple parallel ground pins is positioned parallel to a portion of the first signal pin,
a second leg of the multiple parallel ground pins is positioned parallel to a portion of the second signal pin,
the first leg and the second leg join to form the first single pin contact region at a first end,
the first leg and the second leg join to form the second single pin contact region at a second end,
the first and second signal pins are positioned parallel and are coupled to respective SMT connectors in the first device and respective gold finger connectors in the second device, and
the multiple parallel ground pins provide a 1:N signal to ground ratio for signals transmitted through at least a portion of the first and second signal pins, where N is greater than 1.