US 12,237,457 B2
Vertical solid-state devices
Gholamreza Chaji, Kitchener (CA)
Assigned to VueReal Inc., Waterloo (CA)
Appl. No. 17/614,462
Filed by VueReal Inc., Waterloo (CA)
PCT Filed May 27, 2020, PCT No. PCT/CA2020/050720
§ 371(c)(1), (2) Date Nov. 26, 2021,
PCT Pub. No. WO2020/237373, PCT Pub. Date Dec. 3, 2020.
Claims priority of provisional application 62/853,256, filed on May 28, 2019.
Prior Publication US 2022/0238774 A1, Jul. 28, 2022
Int. Cl. H01L 33/62 (2010.01)
CPC H01L 33/62 (2013.01) [H01L 2933/0066 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An optoelectronic device comprising:
a pad substrate comprising an array of pads connected to a driving circuit;
a device layer structure deposited on a substrate, wherein the device layer structure including a plurality of active layers and conductive layers; and
a pillar layer formed on at least a part of a first conductive layer, wherein the pillar layer is patterned into an array of pillars to create pixelated micro devices, wherein the array of pillars is bonded to the array of pads, and wherein the part of the first conductive layer is patterned in the same pattern as the patterning of the pillar layer.